Titanium incorporation into absorber layer for solar cell

ABSTRACT

A method for fabricating a photovoltaic device includes forming a film including titanium on a conductive layer formed on a substrate. An absorber layer is formed including a Cu—Zn—Sn containing chalcogenide compound with a kesterite structure of the formula: Cu 2-x Zn 1+y Sn(S 1-z Se z ) 4+q  wherein 0≦x≦1; 0≦y≦1; 0≦z≦1; −1≦q≦1 (CZTS) on the film. The absorber layer is annealed to diffuse titanium therein and to recrystallize the CZTS material of the film. A buffer layer is formed on the absorber layer, and a transparent conductive layer is formed on the buffer layer.

RELATED APPLICATION DATA

This application is a Continuation application of co-pending U.S. patentapplication Ser. No. 14/013,827 filed on Aug. 29, 2013, incorporatedherein by reference in its entirety.

BACKGROUND

1. Technical Field

The present invention relates to photovoltaic devices and fabricationmethods, and more particularly to earth-abundant photovoltaic materialhaving a titanium doped absorber layer.

2. Description of the Related Art

Cu₂ZnSnS_(x)Se_(4-x) (CZTS) is a promising earth-abundant photovoltaicmaterial for high-efficiency thin film solar cells. A power conversionefficiency (PCE) of 11.1% has been achieved by Teodor K. Todorov, et al.using a hydrazine-assisted solution approach (Adv. Energy Mater. 3,34-38, 2013). Other vacuum-based and non-vacuum-based depositiontechniques have also been successfully utilized to fabricate CZTS solarcells with PCE above 9%. However, it is very difficult to achieve anefficiency above 11%, and the PCE of CZTS solar cells is still far belowthe physical limit, known as the Shockley-Queisser (SQ) limit, of about29% under terrestrial conditions.

One fundamental reason for the relatively low performance of CZTS solarcells is the large V_(oc) deficit of CZTS devices. V_(oc) deficit refersto the fact that V_(oc) (open circuit voltage) is smaller than expected(e.g., a large V_(oc) deficit corresponds to a smaller-than-expectedV_(oc)). V_(oc) deficit is defined as Eg/q−V_(oc), where Eg/q is theband gap expressed in volts (q is the fundamental charge). Thus far, noeffective method exists that solves the high V_(oc) deficit issue.

SUMMARY

A method for fabricating a photovoltaic device includes forming a filmincluding titanium on a conductive layer formed on a substrate. Anabsorber layer is formed including a Cu—Zn—Sn containing chalcogenidecompound with a kesterite structure of the formula:Cu_(2-x)Zn_(1+y)Sn(S_(1-z)Se_(z))_(4+q) wherein 0≦x≦1; 0≦y≦1; 0≦z≦1;−1≦q≦1 (CZTS) on the film. The absorber layer is annealed to diffusetitanium therein and to recrystallize the CZTS material of the film. Abuffer layer is formed on the absorber layer, and a transparentconductive layer is formed on the buffer layer.

Another method for fabricating a photovoltaic device includes forming aconductive layer on a substrate; forming an absorber layer including aCu—Zn—Sn containing chalcogenide compound with a kesterite structure ofthe formula: Cu_(2-x)Zn_(1+y)Sn(S_(1-z)Se_(z))_(4+q) wherein 0≦x≦1;0≦y≦1; 0≦z≦1; −1≦q≦1 (CZTS) on the conductive layer; doping the absorberlayer with titanium; annealing the absorber layer to recrystallize theCZTS material of the film; forming a buffer layer on the absorber layer;and forming a transparent conductive layer on the buffer layer.

A photovoltaic device includes a substrate having a metal coatingthereon. An absorber layer is formed on the metal coating. The absorberlayer includes a titanium-doped Cu—Zn—Sn containing chalcogenidecompound with a kesterite structure of the formula:Cu_(2-x)Zn_(1+y)Sn(S_(1-z)Se_(z))_(4+q) wherein 0≦x≦1; 0≦y≦1; 0≦z≦1;−1≦q≦1 (CZTS), wherein an atomic percentage of titanium included in theabsorber layer ranges from about 0 to about 0.125. A buffer layer isformed on the absorber layer, and a transparent conductor is formed onthe buffer layer.

These and other features and advantages will become apparent from thefollowing detailed description of illustrative embodiments thereof,which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

The disclosure will provide details in the following description ofpreferred embodiments with reference to the following figures wherein:

FIG. 1 is a cross-sectional view of a photovoltaic device having atitanium layer on which an absorber layer is formed in accordance withthe present principles;

FIG. 2 is a cross-sectional view of a photovoltaic device having anabsorber layer doped with titanium in accordance with the presentprinciples;

FIG. 3 is a graph of SIMS (secondary ion mass spectrometry) elementalprofiles of a finished Ti-incorporating CZTS solar cell fabricated inaccordance with the present principles;

FIG. 4 is a scanning electron microscope (SEM) image showing a top viewof a CZTS film on a Ti/Mo/substrate fabricated in accordance with thepresent principles;

FIG. 5 is a cross-section SEM image of the CZTS film of FIG. 4 inaccordance with the present principles;

FIG. 6 shows X-ray diffraction patterns plotting intensity versus 2θ (2theta) for a CZTS film with Ti incorporated therein and a CZTS film withno-Ti incorporated therein;

FIG. 7 is an external quantum efficiency (EQE) graph for aTi-incorporated CZTS solar cell in accordance with the presentprinciples;

FIG. 8 is a current-voltage graph for a Ti-incorporated CZTS solar celland for a CZTS solar cell without Ti;

FIG. 9 is a diagram comparing V_(oc) deficits of Ti-incorporated CZTSsolar cells and no-Ti CZTS solar cells;

FIG. 10 is a block/flow diagram showing methods for fabricating aphotovoltaic device in accordance with illustrative embodiments; and

FIG. 11 is a block/flow diagram showing other methods for fabricating aphotovoltaic device in accordance with illustrative embodiments.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present principles provide methods and structures that improve opencircuit voltage (V_(oc)) deficits by incorporating elemental titaniuminto Cu₂ZnSnS_(x)Se_(4-x) (CZTS) crystals, films and devices. Thisimproves V_(oc) and power conversion efficiency (PCE) of CZTS solarcells. In one embodiment, a molybdenum-coated substrate is employed.Elemental titanium is introduced into CZTS films by either depositing atitanium layer between CZTS and the Mo-coated substrate or dopingelemental titanium into CZTS films. CZTS films can be deposited byvarious deposition techniques on Mo or Mo/Ti films. An n-typesemiconductor film may be deposited on top of CZTS to form a p-nheterojunction diode. A transparent conductor may be formed on then-type semiconductor with a metallic top contact (e.g., Ni/Al). Thepresent embodiments also include an improved CZTS photovoltaic device,with an efficiency over 11%, which is prepared using the methodsdescribed herein for achieving better V_(oc) performance.

It is to be understood that the present invention will be described interms of a given illustrative architecture having substrates andphotovoltaic stacks; however, other architectures, structures,substrates, materials and process features and steps may be variedwithin the scope of the present invention.

It will also be understood that when an element such as a layer, regionor substrate is referred to as being “on” or “over” another element, itcan be directly on the other element or intervening elements may also bepresent. In contrast, when an element is referred to as being “directlyon” or “directly over” another element, there are no interveningelements present. It will also be understood that when an element isreferred to as being “connected” or “coupled” to another element, it canbe directly connected or coupled to the other element or interveningelements may be present. In contrast, when an element is referred to asbeing “directly connected” or “directly coupled” to another element,there are no intervening elements present.

A design for a photovoltaic device may be created for integrated circuitintegration or may be combined with components on a printed circuitboard. The circuit/board may be embodied in a graphical computerprogramming language, and stored in a computer storage medium (such as adisk, tape, physical hard drive, or virtual hard drive such as in astorage access network). If the designer does not fabricate chips or thephotolithographic masks used to fabricate chips or photovoltaic devices,the designer may transmit the resulting design by physical means (e.g.,by providing a copy of the storage medium storing the design) orelectronically (e.g., through the Internet) to such entities, directlyor indirectly. The stored design is then converted into the appropriateformat (e.g., GDSII) for the fabrication of photolithographic masks,which typically include multiple copies of the chip design in questionthat are to be formed on a wafer. The photolithographic masks areutilized to define areas of the wafer (and/or the layers thereon) to beetched or otherwise processed.

Methods as described herein may be used in the fabrication ofphotovoltaic devices and/or integrated circuit chips with photovoltaicdevices. The resulting devices/chips can be distributed by thefabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged devices/chips), as a bare die, or in a packagedform. In the latter case the device/chip is mounted in a single chippackage (such as a plastic carrier, with leads that are affixed to amotherboard or other higher level carrier) or in a multichip package(such as a ceramic carrier that has either or both surfaceinterconnections or buried interconnections). In any case, thedevices/chips are then integrated with other chips, discrete circuitelements, and/or other signal processing devices as part of either (a)an intermediate product, such as a motherboard, or (b) an end product.The end product can be any product that includes integrated circuitchips, ranging from toys, energy collectors, solar devices and otherapplications including computer products or devices having a display, akeyboard or other input device, and a central processor. Thephotovoltaic devices described herein are particularly useful for solarcells or panels employed to provide power to electronic devices, homes,buildings, vehicles, etc.

It should also be understood that material compounds will be describedin terms of listed elements, e.g., Cu—Zn—Sn—S(Se) (CZTSSe), etc. Thecompounds described herein may include different proportions of theelements within the compound, e.g., Cu_(2-x)Zn_(1+y)Sn(S_(1-z)Se_(z))_(4+q) wherein 0≦x≦1; 0≦y≦1; 0≦z≦1; −1≦q≦1. In addition, otherelements may be included in the compound, such as, e.g., dopants andcrystallization promoters, including but not limited to sodium (Na) andantimony (Sb), and still function in accordance with the presentprinciples. Compositions may optionally include Ge replacing some or allof the Sn, Ag replacing some or all of the Cu, Cd replacing some or allof the Zn, and that may also include dopants, such as, e.g., Sb, Bi, Na,K, Li, Ca, etc. The compounds with additional elements will be referredto herein as alloys.

The present embodiments may be part of a photovoltaic device or circuit,and the circuits as described herein may be part of a design for anintegrated circuit chip, a solar cell, a light sensitive device, etc.The photovoltaic device may be a large scale device on the order of feetor meters in length and/or width, or may be a small scale device for usein calculators, solar powered lights, etc.

It is also to be understood that the present invention may be employedin a tandem (multi-junction) structure. Other architectures, structures,substrate materials and process features and steps may be varied withinthe scope of the present invention. The tandem structure may include oneor more stacked cells.

Reference in the specification to “one embodiment” or “an embodiment” ofthe present principles, as well as other variations thereof, means thata particular feature, structure, characteristic, and so forth describedin connection with the embodiment is included in at least one embodimentof the present principles. Thus, the appearances of the phrase “in oneembodiment” or “in an embodiment”, as well any other variations,appearing in various places throughout the specification are notnecessarily all referring to the same embodiment.

It is to be appreciated that the use of any of the following “/”,“and/or”, and “at least one of”, for example, in the cases of “A/B”, “Aand/or B” and “at least one of A and B”, is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of both options (A andB). As a further example, in the cases of “A, B, and/or C” and “at leastone of A, B, and C”, such phrasing is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of the third listedoption (C) only, or the selection of the first and the second listedoptions (A and B) only, or the selection of the first and third listedoptions (A and C) only, or the selection of the second and third listedoptions (B and C) only, or the selection of all three options (A and Band C). This may be extended, as readily apparent by one of ordinaryskill in this and related arts, for as many items listed.

Referring now to the drawings in which like numerals represent the sameor similar elements and initially to FIG. 1, a method for forming aphotovoltaic structure 10 in accordance with the present principles willbe described. The photovoltaic structure 10 may be employed in solarcells, light sensors, photosensitive devices or other photovoltaicapplications. The structure 10 includes a substrate 12. The substrate 12may include glass or other inexpensive substrate material, such asmetal, plastic or other material suitable for photovoltaic devices(e.g., quartz, silicon, etc.). A conductive layer 14 is formed on thesubstrate 12. The conductive layer 14 may include molybdenum althoughother high work-function materials may be employed (e.g., W, Pt, Au,etc.). The layer 14 provides a metal contact. The conductive layerpreferably includes Mo.

A metal film 15 is deposited on the conductive layer 14 by, e.g., aphysical vapor deposition (PVD) process (e.g., sputtering, evaporation,etc.). The film 15 preferably includes Ti. A thickness of the film 15impacts the amount of titanium available for incorporation into a CZTSabsorber layer 16 to be formed. A Ti layer thickness of between about0.5 nm and about 500 nm may be employed, preferably, between about 5 nmand about 50 nm. The atomic percentage of titanium included in theabsorber layer 16 ranges from about 0 to about 0.125.

The film 15 should be substantially free of any impurities that canadversely affect solar cell performance. Impurities that are known todegrade device performance are iron (Fe) and nickel (Ni), but otherforeign transition metal elements may also serve as recombinationcenters and thereby reduce solar cell performance. Generally, the film15 needs to be prepared from a Ti source that has a purity of 99% orbetter. More preferably, the purity should be 99.9% or better.Optionally, the film 15 may include elements that are known to bebeneficial to device performance. For example, Na or Sb are known to bebeneficial for device performance and may be co-deposited with the film15 in a back layer, such that it can distribute the Na and/or Sb intothe CZTS layer 16 during the film formation process and thereforeimprove device performance.

An absorber layer 16 is formed on the film 15 and includes a Cu—Zn—Sncontaining chalcogenide compound with a kesterite structure of theformula: Cu_(2-x)Zn_(1+y)Sn(S_(1-z)Se_(z))_(4+q) wherein 0≦x≦1; 0≦y≦1;0≦z≦1; −1≦q≦1 (hereinafter CZTS), although other I₂-II-IV-VI₄semiconductors may be employed. Although the major elements in CZTS areCu, Zn, Sn, S, Se, reference to CZTSSe or Cu—Zn—Sn containingchalcogenide material also includes compositions that optionally includeGe replacing some or all of the Sn, Ag replacing some or all of the Cu,Cd replacing some or all of the Zn, and that may also include otherdopants, including Sb, Bi, Na, K, Li, Ca, etc.

In a particularly useful embodiment, the Cu—Zn—Sn-containingchalcogenide includes Cu₂ZnSn(S,Se)₄. In one embodiment, the CZTS filmor layer 16 has a thickness of between about 0.5 microns to about 5microns. Layer 16 may be deposited on the film 15 by any vacuum- orsolution-based deposition method (e.g., painting, sputtering,co-evaporation, electroplating, spin coating, slit casting, doctorblading, dip coating or other simple coating processes). As-preparedCZTS films are subject to annealing under a controlled environment toproduce recrystallized CZTS films.

A controlled environment is employed to react Ti from film 15 with theCZTS film 16. The controlled environment and reaction is one importantfactor for ultimate device performance. The atmosphere used can be achemically inert environment, such as under nitrogen, helium or argon,or it can be a reactive environment, such as one containing sulfurvapor, selenium vapor, hydrogen sulfide, hydrogen selenide, a volatilesulfur-containing compound, a volatile selenium-containing compound, aforming gas, etc. Volatile sulfur-containing compounds may include metalsulfides, carbon disulfide, thiourea, thioacetamide and organic thiolcompounds. Volatile selenium compounds may include metal selenides,carbon diselenide, selenourea and organic selenol compounds.

A temperature profile for the reaction/CZTS recrystallization step needsto be controlled, as well. Heating may be provided by a laboratoryfurnace, tube furnace, rapid thermal processing tool, hot plate, or byother methods known by those skilled in the art. The temperature duringthe heating step may be between about 300° C. and about 800° C. Morepreferably, the temperature is between about 550° C. and about 650° C.

A buffer layer 20 may be formed on layer 16. The buffer layer 20 mayinclude CdS, which forms a high quality junction with layer 16, althoughother materials may be employed, including but not limited to Zn(O,S),ZnO, In₂S₃, (Cd,Zn)S. The buffer layer 20 may include an n-type CdS filmformed on CZTS of layer 16 by a chemical bath deposition. The bufferlayer 20 may include one or more sublayers. For example, the bufferlayer may include distinct sublayers of CdS and intrinsic zinc oxide.

A transparent conductive layer 22 is formed over layer 16 or the bufferlayer 20, if present. The transparent conductive layer 22 may include atransparent conductive oxide (TCO), such as, e.g., aluminum doped zincoxide (AZO), boron doped zinc oxide (BZO), indium tin oxide (ITO) orother TCO materials or combinations thereof.

The deposition process for forming the transparent conductive layer 22may include a sputtering process, an evaporation process, a lowtemperature plasma enhanced chemical vapor deposition (PECVD) process orother suitable deposition process. The transparent conductive layer 22forms a light receiving electrode for the device.

Metal contacts 24, e.g., a Ni/Al multilayer, may be formed on thetransparent conductive layer 22 to further enhance the conductiveproperties of the transparent conductive layer 22. An additionalanti-reflection coating (ARC) (not shown) may also be formed on top ofthe device 10.

Referring to FIG. 2, in another embodiment, the conductive layer 14(e.g., Mo coating on substrate 12) is provided on a photovoltaicstructure 100. An absorber layer 116 is deposited on the conductivelayer 14 by any vacuum- or solution-based deposition method. In thisembodiment, the absorber layer 116 includes Ti as a constituent. Inparticularly useful embodiments, the atomic percentage of titaniumincluded in the absorber layer 116 ranges from about 0 to about 0.125.

The absorber layer 116 includes a Cu—Zn—Sn containing chalcogenidecompound with a kesterite structure of the formula:Cu_(2-x)Zn_(1+y)Sn(S_(1-z)Se_(z))_(4+q) wherein 0≦x≦1; 0≦y≦1; 0≦z≦1;−1≦q≦1 (hereinafter CZTS), although other I₂-II-IV-VI₄ semiconductorsmay be employed. Although the major elements in CZTS are Cu, Zn, Sn, S,Se, reference to CZTSSe or Cu—Zn—Sn containing chalcogenide materialalso includes compositions that optionally include Ge replacing some orall of the Sn, Ag replacing some or all of the Cu, Cd replacing some orall of the Zn, and that may also include other dopants, including Sb,Bi, Na, K, Li, Ca, etc.

In a particularly useful embodiment, the Cu—Zn—Sn-containingchalcogenide includes Cu₂ZnSn(S,Se)₄. In one embodiment, the CZTS filmor layer 116 has a thickness of between about 0.5 microns to about 5microns.

For vacuum-based deposition methods, titanium metal can be incorporatedinto source metal materials or target metal materials which includecopper, zinc and tin metals. For solution-based deposition methods,titanium metal or compounds can be dissolved into precursor solutionswhich include copper, zinc, tin and chalcogens to form CZTS.

Vacuum-based deposition methods for layer 116 may includeco-evaporation, sputtering, laser ablation, flash evaporation and othertechniques known by those skilled in the art. As an example, forco-evaporation, independent elemental Cu, Zn, Sn, Ti, S and SeKnudsen-type sources may be used. The substrate 12 may be maintained atrelatively low temperature (e.g., about 150 degrees C.) during filmdeposition thereby needing a short, e.g., from about 5 min to about 15min, post deposition heat treatment at a high temperature, e.g., fromabout 550 degrees C. to about 650 degrees C., to complete the filmprocessing. Alternatively, the substrate 12 can be maintained at hightemperature during the growth process, in which case it is possible toavoid the need for a high-temperature post-deposition heat treatment.

Solution-based approaches for forming layer 116 may include ahydrazine-assisted method, metal nanoparticles, binary chalcogenidenanoparticles, ternary chalcogenide nanoparticles, quaternary metal saltsolutions, electrodeposition, hydrothermal methods, and other techniquesknown by those skilled in the art. As an example, for thehydrazine-assisted method, elemental Cu, Zn, Sn, Ti or Ti-containingcompounds, S and Se powders may be dissolved or dispersed in purehydrazine. An obtained colloid solution may be deposited on theconductive layer 14 by spin casting, followed by a post deposition heattreatment at high temperature, e.g., from about 550 degrees C. to about650 degrees C., to complete the film processing. Ti-containing compoundsmay include elemental titanium, titanium halides, titaniumchalcogenides, titanium oxide, titanium isopropoxide, Ammoniumbis(oxalato)oxotitanate(IV) and other organic titanium-containingcompounds.

As-prepared CZTS films are subject to annealing under a controlledenvironment to produce recrystallized CZTS films. The atmosphere usedcan be a chemically inert environment, such as under nitrogen, helium orargon, or it can be a reactive environment, such as one containingsulfur vapor, selenium vapor, hydrogen sulfide, hydrogen selenide, avolatile sulfur-containing compound, a volatile selenium-containingcompound, a forming gas, etc. Volatile sulfur-containing compounds mayinclude metal sulfides, carbon disulfide, thiourea, thioacetamide andorganic thiol compounds. Volatile selenium compounds may include metalselenides, carbon diselenide, selenourea and organic selenol compounds.

A temperature profile for the CZTS recrystallization step needs to becontrolled. Heating may be provided by a laboratory furnace, tubefurnace, rapid thermal processing tool, hot plate, or by other methodsknown by those skilled in the art. The temperature during the heatingstep may be between about 300° C. and about 800° C. More preferably, thetemperature is between about 550° C. and about 650° C.

The buffer layer 20 may be formed on layer 116. The buffer layer 20 mayinclude CdS, which forms a high quality junction with layer 116,although other materials may be employed, including but not limited toZn(O,S), ZnO, In₂S₃, (Cd,Zn)S. The buffer layer 20 may include an n-typeCdS film formed on CZTS of layer 16 by a chemical bath deposition. Thebuffer layer 20 may include one or more sublayers. For example, thebuffer layer may include distinct sublayers of CdS and intrinsic zincoxide.

The transparent conductive layer 22 is formed over layer 116 or thebuffer layer 20, if present. The transparent conductive layer 22 mayinclude a transparent conductive oxide (TCO), such as, e.g., aluminumdoped zinc oxide (AZO), boron doped zinc oxide (BZO), indium tin oxide(ITO) or other TCO materials or combinations thereof.

The deposition process for forming the transparent conductive layer 22may include a sputtering process, an evaporation process, a lowtemperature plasma enhanced chemical vapor deposition (PECVD) process orother suitable deposition process. The transparent conductive layer 22forms a light receiving electrode for the device.

Metal contacts 24, e.g., Ni/Al, may be formed on the transparentconductive layer 22 to further enhance the conductive properties of thetransparent conductive layer 22. An additional anti-reflection coating(ARC) (not shown) may also be formed on top of the device 100.

In accordance with the present principles, a Ti-substituted absorber isemployed to improve open circuit voltage and power conversion efficiency(PCE). The following are non-limiting illustrative examples describingimplementations of exemplary embodiments.

Example 1

For making Ti-free devices, solution A (3.3M Cu₂S) was made bydissolving Cu and S in hydrazine. Similarly, Sn and Se were stirred inhydrazine to form slurry B (1.5 M SnSe_(s)); Solution A and slurry Bwere mixed together and transferred to a vial containing zinc formate,yielding solution C with final composition Cu/(Zn+Sn)=0.8, Zn/Sn=1.22and nominal kesterite CZTSSe concentration of approximately 0.4 M. Thethin film CZTS absorber layer with final thickness of 2-2.5 microns wasprepared by spin coating this mixture over six consecutive layers at 600rpm and then subsequently subjecting it to a short anneal on a ceramichot plate with a set point of 630 degrees C.

The CdS buffer, ZnO window, and indium doped tin oxide (ITO) layers weresubsequently deposited by chemical bath deposition and RF magnetronsputtering, respectively, giving a CZTSSe device structure with a devicearea of approximately 0.45 cm², as defined by mechanical scribing. ANi/Al collection grid and 110-nm-thick MgF₂ antireflection coating weredeposited on top of the device by electron-beam evaporation. Example 1describes a preparation and characteristics of a CZTS solar cell withoutTi (graph 204) having a PCE equal to 10.03% shown in FIG. 8.

Example 2

For making Ti-incorporating devices, a solution A (3.3M Cu₂S) was madeby dissolving Cu and S in hydrazine. Similarly, Sn and Se were stirredin hydrazine to form slurry B (1.5 M SnSe_(s)); Solution A and slurry Bwere mixed together and transferred to a vial containing zinc formate,yielding solution C with final composition Cu/(Zn+Sn)=0.8, Zn/Sn=1.22and nominal kesterite CZTSSe concentration of approximately 0.4 M. A 20nm titanium thin film was deposited on molybdenum-coated glass byelectron-beam evaporation. The Ti- and Mo-coated glass was used as asubstrate for CZTS deposition.

The thin film CZTS absorber layer with final thickness of 2-2.5 micronswas prepared by spin coating this mixture over six consecutive layers at600 rpm and then subsequently subjecting it to a short anneal on aceramic hot plate with a set point of 630 degrees C. The CdS buffer, ZnOwindow, and indium doped tin oxide (ITO) layers were subsequentlydeposited by chemical bath deposition and RF magnetron sputtering,respectively giving a CZTSSe device structure with a device area ofapproximately 0.45 cm², as defined by mechanical scribing. A Ni/Alcollection grid and 110-nm-thick MgF₂ antireflection coating weredeposited on top of the device by electron-beam evaporation. Example 2describes a preparation and characteristics of a Ti-incorporated CZTSsolar cell (graph 202) having a PCE equal to 11.14% shown in FIG. 8.

Referring to FIG. 3, a graph of SIMS (secondary ion mass spectrometry)elemental profiles of a finished Ti-incorporating CZTS solar cellfabricated by methods described above is illustratively depicted. Thegraph plots intensity (counts per second (C/s)) versus time (seconds).As shown, a strong Ti feature 102 is formed at the CZTS/Mo interfacethat indicates the presence of Ti accumulation at the CZTS/Mo interface.Ti is uniformly doped throughout entire CZTS film with a pile-up feature104 around the CdS emitter/ZnO interface.

Referring to FIG. 4, a scanning electron microscope (SEM) image shows atop view of a CZTS film on a Ti/Mo/substrate fabricated in accordancewith the present principles. Micrometer-sized CZTS grains are uniformlydistributed as indicated in the image. A 10-micron scale 112 isindicated in FIG. 4.

Referring to FIG. 5, a cross-section SEM image of the CZTS film of FIG.4 is shown. The thicknesses of the CZTS layer 16 and the Mo layer 14 are2.136 microns and 379.6 nm, respectively. An 89.32 nm MoSe₂ layer 17 isformed during the annealing process. SIMS elemental profiles show thatthe Ti and MoSe₂ are chemically mixed after annealing.

Referring to FIG. 6, X-ray diffraction patterns plotting intensityversus 2θ (2 theta) are shown for a CZTS film with Ti incorporatedtherein and no-Ti incorporated therein. Both CZTS films showkesterite-type structures. No obvious structural differences weredetected between these two CZTS films in the X-ray diffractions.

Referring to FIG. 7, an external quantum efficiency (EQE) graph is shownfor a Ti-incorporated CZTS solar cell. The maximum EQE is 96% for 570 nmwavelength light. The band gap determined at the absorption edge is 1.14eV.

Referring to FIG. 8, a current-voltage graph is shown for aTi-incorporated CZTS solar cell 202 and a CZTS solar cell without Ti204. The Ti-incorporated CZTS solar cell 202 has a 1.14 eV band gapwhile CZTS solar cell without Ti 204 has a 1.16 eV bandgap. In thisexample, due to the incorporation of Ti into the CZTS solar cell (202),the PCE rises to 11.14% as compared to 10.03% for the CZTS solar cellwithout Ti 204. The Ti incorporation into the CZTS not only boostsV_(oc) but also improves the current collection, resulting in highershort circuit current (J_(sc)) and V_(oc), which increase by 1.44 mA/cm²and 25 mV, respectively.

Referring to FIG. 9, a diagram is shown comparing the V_(oc) deficits(E_(g)/q−V_(oc)) of Ti-incorporated CZTS solar cells and no-Ti CZTSsolar cells. The graph shows V_(oc) deficit (mV) versus energy gap (eV).The graph clearly demonstrates the benefit of Ti incorporation into CZTSfrom the aspect of V_(oc) enhancement. The present embodiments havesignificant potential to reduce V_(oc) deficit and push the efficiencyof CZTS solar cells towards the SQ limit.

Referring to FIGS. 10 and 11, it should also be noted that, in someimplementations, the functions noted in the blocks may occur out of theorder noted in FIGS. 10 and 11. For example, two blocks shown insuccession may, in fact, be executed substantially concurrently, or theblocks may sometimes be executed in the reverse order, depending uponthe functionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts, or combinations of special purpose hardware andcomputer instructions.

Referring to FIG. 10, methods for fabricating a photovoltaic device areillustratively shown. In block 302, a substrate is provided with aconductive layer formed thereon. In one example, the substrate includesglass, and the conductive layer may include Mo. Other materials may alsobe employed. In block 304, a film including titanium is formed on theconductive layer. In block 306, the film is formed from a titaniumsource that has a purity of 99% or greater. In block 308, the film isco-formed with an additional element source that includes beneficialelements such as sodium and/or antimony.

In block 310, an absorber layer is formed including a Cu—Zn—Sncontaining chalcogenide compound with a kesterite structure of theformula: Cu_(2-x)Zn_(1+y)Sn(S_(1-z)Se_(z))_(4+q) wherein 0≦x≦1; 0≦y≦1;0≦z≦1; −1≦q≦1 (CZTS) on the film.

In block 312, a vacuum-based deposition may be performed by one ofco-evaporation, sputtering, laser ablation, flash evaporation, etc. Inblock 314, a solution-based deposition may be performed by one of ahydrazine-assisted solution, metal nanoparticles, binary chalcogenidenanoparticles, ternary chalcogenide nanoparticles, quaternary metal saltsolutions, electrodeposition, a hydrothermal method, etc.

In block 316, the absorber layer is annealed to diffuse titanium thereinand to recrystallize the CZTS material of the film. In block 318, theabsorber layer is annealed in a controlled environment to produce arecrystallized CZTS film. The controlled environment includes one of achemically inert environment and a reactive environment. The annealincludes heating the absorber layer to between about 300° C. and about800° C.

In block 320, a buffer layer is formed on the absorber layer. In block322, a transparent conductive layer is formed on the buffer layer. Metalcontacts, anti-reflection coatings, etc. may also be formed.

Referring to FIG. 11, methods for fabricating a photovoltaic device areillustratively shown. In block 402, a substrate is provided with aconductive layer formed thereon. In one example, the substrate includesglass, and the conductive layer may include Mo. Other materials may alsobe employed. In block 404, an absorber layer is formed on the conductivelayer including a Cu—Zn—Sn containing chalcogenide compound with akesterite structure of the formula:Cu_(2-x)Zn_(1+y)Sn(S_(1-z)Se_(z))_(4+q) wherein 0≦x≦1; 0≦y≦1; 0≦z≦1;−1≦q≦1 (CZTS). In block 406, a vacuum-based deposition is performed byone of co-evaporation, sputtering, laser ablation, and flashevaporation. In block 408, a solution-based deposition is performed byone of a hydrazine-assisted solution, metal nanoparticles, binarychalcogenide nanoparticles, ternary chalcogenide nanoparticles,quaternary metal salt solutions, electrodeposition, and a hydrothermalmethod.

In block 410, the absorber layer is doped with titanium. In block 412,titanium is incorporated in one of source metal materials and targetmetal materials during the formation of the absorber layer in avacuum-based deposition. In block 414, titanium is incorporated usingone of titanium metal and titanium compounds dissolved into precursorsolutions in a solution-based deposition.

In block 416, the absorber layer is annealed to recrystallize the CZTSmaterial of the film. In block 418, the absorber layer is annealed in acontrolled environment to produce a recrystallized CZTS film. Thecontrolled environment includes one of a chemically inert environmentand a reactive environment. The anneal includes heating the absorberlayer to between about 300° C. and about 800° C.

In block 420, a buffer layer is formed on the absorber layer. In block422, a transparent conductive layer is formed on the buffer layer. Metalcontacts, anti-reflection coatings, etc. may also be formed.

Having described preferred embodiments for titanium incorporation intoan absorber layer for a solar cell (which are intended to beillustrative and not limiting), it is noted that modifications andvariations can be made by persons skilled in the art in light of theabove teachings. It is therefore to be understood that changes may bemade in the particular embodiments disclosed which are within the scopeof the invention as outlined by the appended claims. Having thusdescribed aspects of the invention, with the details and particularityrequired by the patent laws, what is claimed and desired protected byLetters Patent is set forth in the appended claims.

What is claimed is:
 1. A photovoltaic device, comprising: a substratehaving a metal coating thereon; an absorber layer formed on the metalcoating, the absorber layer including a titanium-doped Cu—Zn—Sncontaining chalcogenide compound with a kesterite structure of theformula: Cu_(2-x)Zn_(1+y)Sn(S_(1-z)Se_(z))_(4+q) wherein 0≦x≦1; 0≦y≦1;0≦z≦1; −1≦q≦1 (CZTS), wherein an atomic percentage of titanium includedin the absorber layer ranges from about 0 to about 0.125; a buffer layerformed on the absorber layer; and a transparent conductor formed on thebuffer layer.
 2. The device as recited in claim 1, further comprising atitanium containing layer disposed between the absorber layer and themetal coating.
 3. The device as recited in claim 2, wherein the titaniumcontaining layer includes a thickness of between about 0.5 nm and about500 nm.
 4. The device as recited in claim 1, further comprising an opencircuit voltage deficit of less than about 670 mV.
 5. The device asrecited in claim 1, wherein the device includes a power conversionefficiency (PCE) of greater than 11.0%.